(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of providing a coating of Photoresist Protect Oxide (RPO) such that the occurrence of polysilicon void defects is eliminated.
(2) Description of the Prior Art
The creation of CMOS devices is well known and well established in the art. Continued miniaturization of device features, in order to gain improved device performance at a competitive cost, leads to continued reduction in device feature size and with that a continued reduction in the thickness of the various layers of semiconductor material that are used in the creation of a semiconductor device.
During the formation of CMOS devices over the surface of a substrate, devices of different polarities, such as CMOS and NMOS devices, can be created overlying the surface of one substrate and as part of a continuing processing stream. Also, some of these different devices may be processed following a different processing stream, for instance some of the devices may by provided with salicided, low resistivity points of contact to the gate electrodes of the CMOS devices while other devices that are also created over the surface of the same substrate are not processed with salicided points of electrical contact to the CMOS devices. For this reason, that is the difference in processing steps for CMOS devices that are created over the surface of one substrate, some of these devices are coated with a layer of (photo) Resistance Protective Oxide (RPO).
As an example of the difference in processing of CMOS devices that are created over the surface of one substrate can be cited the creation of self-aligned contact points to the source/drain regions and the gate electrode of a CMOS device. By universally covering all CMOS devices that are created over the surface of the substrate with a layer of RPO after the gate structures, including the gate spacers, have been created, the devices can be divided into devices that need to be provided with salicided points of electrical contact and those that do not. By then covering the devices that do not need to be provided with salicided points of contact with a patterned layer of photoresist that covers these devices, the layer of RPO can be removed from the devices which need to be provided with salicide points of electrical contact, thus exposing the surfaces that need to be salicided and enabling the completion of the salicidation for the devices that are not covered by a layer of photoresist.
With the continuing decrease in device feature size, the thickness of this layer of RPO also needs to be further decreased, which places increased demands on the quality of the layer of RPO that is deposited. The quality of the layer of RPO is typically evaluated using parameters such as Field-to-Breakdown (Vbd) and Charge-to-Breakdown (Qbd). One of the problems that is encountered in the era of sub-micron device feature size is the occurrence of voids in the interface between the layer of RPO and the layer of polysilicon that is used for the creation of the gate structure. It is critical that the occurrence of such voids is prevented, the invention provides such a method by controlling the quality of the layer of RPO that is used.
U.S. Pat. No. 6,207,492 (Tzeng et al.) shows a RPO layer.
U.S. Pat. No. 6,174,590 (Iyer et al.) and U.S. Pat. No. 6,162,722 (Hsu) shows silicon rich oxide ARC layers.
U.S. Pat. No. 6,194,258 (Wuu) and U.S. Pat. No. 6,187,655 (Wang) are related patents.
A principle objective of the invention is to provide a method that prevents the formation of voids in the interface between a layer of Resist Protect Oxide (RPO) and an underlying layer of polysilicon that functions as a layer of a gate structure.
In accordance with the invention, a new layer of RPO is provided for semiconductor devices, specifically for semiconductor devices having sub-micron device feature size. The layer of RPO that is provided by the invention comprises a layer of silicon-rich CVD oxide, having a refractive index of between about 1.57 and 1.60, to prevent silicon atoms that are present in a layer of polysilicon from diffusing into the overlying layer of resist protect oxide.